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State machine/general verilog issues

 
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Johneames
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Joined: 14 Oct 2017
Posts: 133

PostPosted: Mon Nov 27, 2017 11:19 am    Post subject: State machine/general verilog issues Reply with quote

hello,

I'm trying to code a verilog system that gets data from a PC over uart, then stores that data in a fifo and reads the stored data out of the fifo when commanded by a specific uart byte. However I have been having many issues, first of which is when I send the byte that should enable the state that writes to the fifo, nothing seems to happen. Another slighltey less important issue is that I have no idea how to create a testbench that would properly stimulate the uart data line.

Please help.
Thanks!

I didn't find the right solution from the Internet.

References:
https://forums.xilinx.com/t5/Welcome-Join/State-machine-general-verilog-issues/td-p/399857


industrial product animation
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